Compressor Logic of EDT Architecture

DFT Basics : Article #17

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In the previous five blogs of this DFT Basics series, we explored the complete EDT (Embedded Deterministic Test) architecture in detail. In this blog, we will take a closer look at the compressor component specifically.

This post is in response to a reader’s request, and we’ll use simplified illustrations to help explain how the compressor works within the EDT architecture.

Let’s get started !

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Compressor (or) Compactor :

Compressor, compresses the values of all scan chains to a single value.
Compressor has levels of XORs.

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In this blog, we have used simplified illustrations to explore the working of compressor within the EDT architecture.
In my next series of blogs, we will explore Automatic Test Pattern Generation (ATPG).

Stay Tuned !