Yes. In hierachical scan, the OCCs will be placed in that way.
In the case which you are asking (it will be intest of TOP and extest of sub-block case), there sub-block's OCC will be transparent (tm = 0). So whatever clock is propagated by TOP OCC will transparently pass through sub-block OCC and go to the wrapper flops of sub-block as sub-blocks' OCC is transparent.
For diagrammatic explanation, you can check in the intest of TOP and extest of sub-block topic in placement of OCC topic.
If I wish to program an OCC to generate 2 pulses during capture, so the number of 1s in shift reg should be 2 . how does these 1s are set in the shift reg? is it done during shift ?
I came across tessent OCC where it has a signal named "capture_cycle_width"? any idea?
I also came across the words synchronous OCCs and asynchronous OCCs, could also through some light on this?
I wanted to ask, how do we cover the faults on the Functional enable pin of any clock-gaters, as the output of any clock gater is either slow or fast clock only and not logic value which I observed on scan flop.
I will discuss that in the ATPG topic.
I will discuss that when I cover the advantages of connecting TE of ICG to Scan Enable signal
Hi Shri,
Yes. In hierachical scan, the OCCs will be placed in that way.
In the case which you are asking (it will be intest of TOP and extest of sub-block case), there sub-block's OCC will be transparent (tm = 0). So whatever clock is propagated by TOP OCC will transparently pass through sub-block OCC and go to the wrapper flops of sub-block as sub-blocks' OCC is transparent.
For diagrammatic explanation, you can check in the intest of TOP and extest of sub-block topic in placement of OCC topic.
thanks vidisha, the blog explained it , I put the question without completing the blog. Very nicely explained
If I wish to program an OCC to generate 2 pulses during capture, so the number of 1s in shift reg should be 2 . how does these 1s are set in the shift reg? is it done during shift ?
I came across tessent OCC where it has a signal named "capture_cycle_width"? any idea?
I also came across the words synchronous OCCs and asynchronous OCCs, could also through some light on this?
Hi Vidisha,
I wanted to ask, how do we cover the faults on the Functional enable pin of any clock-gaters, as the output of any clock gater is either slow or fast clock only and not logic value which I observed on scan flop.