Yes, you are correct, in order to take atspeed coverage, we place Xor gate as fanout to q-d loopback and one input to that fanout is through some tdr or constraint logic.
Lets consider the input wrapper chain. For the input wrapper cells the SE=1, I mean all the wrapper flops are always be in shift mode. They dont capture.
If I am using shared wrapper cell of my design, then that flop needs to capture data during capture mode, then how can we control the shift and capture mode operation of that particular shared wrapper flop?
For input side wrapper chains (shared input wrapper)
shift phase => shifting operation will happen
capture phase (in int mode runs) => it will retain it's last shifted value
capture phase (in ext mode runs) => it will capture the value at the fn input pin (because se = top level se or int_ltest_en ---> se = 0 or 0 --> se = 0 --> D input is selected)
Therefore, During ext mode run capture phase, input side wrapper flops will capture the value at it's D pin (fn input port value)
Role of Input side wrappers :
In int mode runs => launch data to inside logic (last shifted value will control the combo)
In ext mode runs => capture data from outside logic (capture the value at the fn input port)
One interesting point here is the case you mentioned - when there is no combinational logic between the PI and shared input wrapper cell.
In the case there is combinational logic between the PI and the shared input wrapper cell, that the combinational logic will be test at external mode . So during the capture phase , it still retain value its last shift value too.
Thank you for the detailed post!
A question on the wrapper cell:
There could be a XOR gate on the Q-D loopback for wrapper cell, to enable at-speed coverage.
What is the tdr value ?
Yes, you are correct, in order to take atspeed coverage, we place Xor gate as fanout to q-d loopback and one input to that fanout is through some tdr or constraint logic.
Thanks for sharing this post.
I have some confusion about the function of the wrapper cell and boundary scan.
In the SoC hierarchical scan view, one of the benefits of the wrapper cell is to check the interconnection between block levels.
As I understand, boundary scan is used to check the interconnection at the board level.
So, boundary scan insertion is mainly done to enable board-level testing, right? I mean at the SoC level, it’s just prepared for board-level testing.
Yes
Thanks you
I just have a small question:
Lets consider the input wrapper chain. For the input wrapper cells the SE=1, I mean all the wrapper flops are always be in shift mode. They dont capture.
If I am using shared wrapper cell of my design, then that flop needs to capture data during capture mode, then how can we control the shift and capture mode operation of that particular shared wrapper flop?
For input side wrapper chains (shared input wrapper)
shift phase => shifting operation will happen
capture phase (in int mode runs) => it will retain it's last shifted value
capture phase (in ext mode runs) => it will capture the value at the fn input pin (because se = top level se or int_ltest_en ---> se = 0 or 0 --> se = 0 --> D input is selected)
Therefore, During ext mode run capture phase, input side wrapper flops will capture the value at it's D pin (fn input port value)
Role of Input side wrappers :
In int mode runs => launch data to inside logic (last shifted value will control the combo)
In ext mode runs => capture data from outside logic (capture the value at the fn input port)
One interesting point here is the case you mentioned - when there is no combinational logic between the PI and shared input wrapper cell.
In the case there is combinational logic between the PI and the shared input wrapper cell, that the combinational logic will be test at external mode . So during the capture phase , it still retain value its last shift value too.
In most of the designs mux selection will be capture_en.
Capture_en and se is same just naming sake or both are different, can you please clarify on it