Scan Wrappers and Hierarchical Scan (Part 1)

DFT Basics : Article #19

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In the previous 18 articles of the DFT Basics series, we explored topics such as Scan Insertion, Scan Compression, On-Chip Clock Controller, and ATPG Pattern Generation. In the upcoming posts, we will continue our discussion on ATPG concepts, including coverage analysis and improvement.

In this blog, however, let’s take a brief detour from the ATPG topic and explore the concept of Hierarchical Scan.

Let’s get Started !

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Flat Vs Hierarchical Scan

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Let’s explore Hierarchical Scan concepts using the below design :

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Wrapper Insertion (we will explore w.r.t CoreA level)

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Wrapper Chains

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Types of Wrapper Cells

< < Note : PI stands for Primary Input (functional input) and PO stands for Primary Output (functional output)> >

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Dedicated Wrapper Cell

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Shared Wrapper Cell

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Let’s explore Shared Input Wrapper Cell !

Note :
se is Scan Enable. It will be a top level port.
int_ltest_en will be controlled by TDR

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Shift Phase :

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Capture Phase : (int mode)

< < In int_mode, only the logic internal to the block will be active. Logic external to the block will not be active. It will be X > >

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Capture Phase : (ext mode)

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Let’s explore Shared Output Wrapper Cell !

Note :
se is Scan Enable. It will be a top level port.
ext_ltest_en will be controlled by TDR

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Shift Phase :

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Capture Phase : (int mode)

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Capture Phase : (ext mode)

< < In ext_mode, the logic internal to the block will not be active. It will be X > >

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Let’s explore Dedicated Input Wrapper Cell !

Note :
se is Scan Enable. It will be a top level port.
int_ltest_en will be controlled by TDR

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Shift Phase :

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Capture Phase : (int_mode)

< < In int_mode, only the logic internal to the block will be active. Logic external to the block will not be active. It will be X > >

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Capture Phase : (ext_mode)

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Let’s explore Dedicated Output Wrapper Cell !

Note :
se is Scan Enable. It will be a top level port.
ext_ltest_en will be controlled by TDR

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Shift Phase

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Capture Phase : (int mode)

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Capture Phase : (ext mode)

< < In ext_mode, the logic internal to the block will not be active. It will be X > >

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Let’s summarize the points which we explored above

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Wrapper Chains

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References :

• Tessent Scan and ATPG user’s manual

• Wrapper Chains by Semicon shorts

• Integrating Wrapped Cores in a Compressed Scan Flow - From Solvnet

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In this post, we explored the concept of Scan Wrappers. Building on this foundation, our next post will cover Hierarchical Scan concepts, including INTEST, EXTEST, and pattern re-targeting.

Stay tuned for the next post, coming this Tuesday!